Various methods have been proposed for electrically connecting the bonding pads of an integrated microcircuit and the external package leads, as well as providing physical support and protective housing for the circuit. Traditionally, this connection has been achieved by establishing a very fine wire contact between a bonding pad of the semiconductor device and a narrow lead finger of a lead frame, where the lead frame finger gradually widens and becomes substantial enough to form the external package leads. These wire bonding techniques involve the thermocompression and thermosonic bonding of extremely fine wires to the points to be interconnected. However, this method is time-consuming and expensive, particularly when it is realized that for a 64-lead device, for example, 128 separate bonding steps are needed, each of which requires the careful positioning of the partially assembled device in the bonding apparatus.
An alternate approach is to directly bond the bonding pads of the integrated circuit chip with the interior terminals of the die support frame. In the discussion of the art and the invention herein, the term "die support frame" will be used as a generic term meaning any support frame, chip interconnection armature, etc. for an integrated circuit chip that involves any kind of metallized interconnection between the integrated circuit die and the exterior package. Thus a die support frame could be a lead frame in the traditional sense of that term or the die support frame could be the body of a chip carrier package or any standard package made of ceramic or plastic having leads formed thereon or the die support frame could be a glass plate, as in the instance where integrated circuits are directly used to provide electronic displays where the chip is electrically connected to leads borne by the glass.
As integrated circuit technology advanced, requiring more electronic devices on a smaller silicon chip, other possibilities for connecting to the semiconductor bonding pads were explored. One method which has gained wide acceptance, at least for relatively low lead-count semiconductor devices, is tape automatic bonding or TAB. This technique involves making flexible lead carrier tape having a photo-lithographically produced printed circuit pattern of conductive flexible foil thereon which is very accurate. In contrast to the lead frame thickness, the thickness of the TAB foil leads is typically in the range of about 0.5 to 2.0 mil, often about 1.4 mil. This reduced size permits TAB foil leads to be used on smaller, more closely spaced bonding pads of the increased density integrated circuits. For an overview of tape automated bonding technology, see T. G. O'Neill, "The Status of Tape Automated Bonding", Semiconductor International, February, 1981, pp. 33-51.
One of the requirements of TAB bonding is that there must be a small quantity of bonding or interconnecting material, commonly called a "bump" on either the bonding pad of the integrated circuit die or on the interior terminals of the TAB foil pattern leads. The bumps are typically gold or solder bumps that are electroplated onto the bonding pads. There has been some success with using the bumped tape to bond onto bonding pads of die which have no bumps. However, a considerable drawback to the TAB process is that of the high cost of learning to place bumps on the chip bonding pads or the TAB tape. Even after one has become accomplished at it, the bumping process can be expensive.
Thus, it would be desirable if a process could be developed whereby bumps could be formed on the bonding pads of a semiconductor die or on the TAB tape inexpensively. Even if such a process were time consuming, it would be advantageous to use for devices having low quantities but high per unit cost, or in further research and development of chip bonding processes.